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Generated by 🚫 dangerJS against b333d4c

Memory usage test (comparing PR against master branch)

The table below shows the summary of memory usage change (decrease - increase) in bytes and percentage for each target.

Test Results

 76 files   76 suites   15m 47s ⏱️
 38 tests  38 ✅ 0 💤 0 ❌
241 runs  241 ✅ 0 💤 0 ❌

Results for commit b333d4c.

♻️ This comment has been updated with latest results.

Please add a check for IDF versions greater than 5.3:

https://github.com/espressif/arduino-esp32/actions/runs/19442524813/job/55629051409?pr=12038

On P4 EV Board card is no longer mounting with the changes in PR.

@lbernstone If I comment out the UHS-1 flag, the sdmmc starts working again and the speed is improved with the DDR flag only.

@P-R-O-C-H-Y What kind of SD card do you have?
Does it have UHS markings on the card or is it just a SDHC/SDXC card? (or even just SD, which is really a collectors item these days)

@P-R-O-C-H-Y What kind of SD card do you have? Does it have UHS markings on the card or is it just a SDHC/SDXC card? (or even just SD, which is really a collectors item these days)

Its a Kingston 16GB with USH-1 marking on it.

Weird is, that the SD card is not working on the P4-EYE board I got. Even with/without the changes in this PR.

Can you try to format it using some SD-format tool?
Or format it using some non-PC device like a camera.
It might be the partitioning is unconventional and/or the file system already present is not supported by the libraries we use.
Or maybe the "P4 EYE" doesn't use all 4 pins? For example DAT3 is wired as card detection?

The P4-eye have identical SD card schema as the P4-EV board. Will try with formatted card and also with different one.

Maybe also try some SDHC/SDXC card?
Those UHS cards may want to negotiate a lower signal level of 1V8. Not sure if this is expected or required. I know it is a feature of the standard.

in all cases, we want to support more cards, not less. If these options make cards not work, we need to make them optional

I'm not sure if SDHC uses DDR signalling.
If I'm not mistaken, this was initially only a protocol update to support cards > 2 GB.
There is a "high speed" variant for SDHC/XC/UC which doubles the bus speed, so I guess that does look like DDR.

Looking here: https://www.sdcard.org/developers/sd-standard-overview/bus-speed-default-speed-high-speed-uhs-sd-express/
I see there is a 50 MHz and 104 MHz signalling for UHS-I, where there doesn't seem to be a DDR104.
I have no idea what frequency is being used here?

I'll see if I can find some old cards around here and test an array of them. Not sure if I have really small & slow ones around any more.

Weird is, that the SD card is not working on the P4-EYE board I got. Even with/without the changes in this PR.

P4-eye (waveshare) has BOARD_SDMMC_POWER_PIN on 46

Hmm I took another look at the source code of this PR and

host.flags &= ~SDMMC_HOST_FLAG_DDR;

looks like it is disabling DDR?
If so then I am quite curious to why it is improving the speed.

If it is indeed increasing the transfer speed, then it sounds like a timing issue, or maybe some signal is inverted?

Hmm these defines for sure would be a lot more clear with quite a bit more comments...
https://github.com/espressif/esp-idf/blob/8f1e7bc4e08878f5a2aab55fdf302789d3a3eac4/components/sdmmc/include/sd_protocol_types.h#L198-L205

#define SDMMC_FREQ_DEFAULT      20000       /*!< SD/MMC Default speed (limited by clock divider) */
#define SDMMC_FREQ_HIGHSPEED    40000       /*!< SD High speed (limited by clock divider) */
#define SDMMC_FREQ_PROBING      400         /*!< SD/MMC probing speed */
#define SDMMC_FREQ_52M          52000       /*!< MMC 52MHz speed */
#define SDMMC_FREQ_26M          26000       /*!< MMC 26MHz speed */
#define SDMMC_FREQ_DDR50        50000       /*!< MMC 50MHz speed */
#define SDMMC_FREQ_SDR50        100000      /*!< MMC 100MHz speed */
#define SDMMC_FREQ_SDR104       200000      /*!< MMC 200MHz speed */

The names of those defines don't appear to match the frequency numbers.
I assume the "DDR50", "SDR50" and "SDR104" refer to the bus speeds on this page
If so, then both DDR50 and SDR50 refer to 50 MByte/sec.
And since there are 4 bits per transfer on UHS-I cards (not sure about the others as they do have 2 rows of pads, always thought those were for differential signalling, but not 100% sure), you need 2 transfers per byte.
So for SDR50 -> 100 MHz and DDR50 -> 50MHz

Then the most important change of this PR is setting the clock?
And then not disabling DDR and setting the max. freq to SDMMC_FREQ_DDR50 would result in the same speed improvement, right?
Likely with less RF noise and better timings.